electronics

A model node in Electronics mode holds a whole circuit: the schematic, the netlist it produces, the board, and a 3D view of the board. They are one chain of steps, so changing a part on the schematic reaches the board and the exports.

Your pixie can build the chain for you; this page covers what you can drive by hand and what each check tells you.

the three modes

Open the mode picker in the editor's top bar and choose Electronics:

mode	what you do there
Schematic	Symbols, wires, SPICE simulation
PCB layout	Place parts and route the board
Fab outputs	Gerber, drill and netlist exports, plus a cost estimate

Every step is an operation in the node's timeline. A dot shows its state: green ok, amber warning, red error.

draw a wired schematic

In Schematic the ribbon offers Place symbol, Wire, Net label, Power, Junction and No connect, then Annotate (numbers the reference designators), ERC, Netlist and Simulate.

The netlist is read from what is drawn. A pin lying on a wire joins it, and pins carrying the same net label join. To join a pin to a net without a wire, give that pin the net name.

Built-in symbols cover passives, diodes, LEDs, transistors, a crystal, switches, test points, SPICE sources and pin headers up to 40 pins. For anything else a pixie writes a box symbol from a pin list, up to 400 pins.

ERC checks the sheet. Open its panel to read each marker. A pixie can also pass an intent: the rail voltages, pull-up range, bus addresses and pin-to-net rules you meant. The check flags where the sheet disagrees; it never rewrites your circuit.

parts

Ask a pixie to find a part and it searches in two ways:

• by LCSC number: it reads the part's footprint and symbol and hands them over ready to place;
• by spec: "a 100 nF 50 V X7R 0402" is matched against ixi's own part catalogue, ranked by basic parts first, then price and stock. If nothing fits, it says which single requirement came closest to missing, instead of quietly relaxing one.

lay out the board

In PCB layout, start with New board. Choose the outline, then Forward annotate pulls the schematic's parts and nets onto it. The layout step holds the position, side and turn of every footprint. The Layout panel lists footprints with editable x and y and a side toggle.

Ribbon tools: Move footprint, Flip footprint, Route, Via, Zone, Outline.

A board has two copper layers by default. The Stack panel adds the inner pair: "make it a 4-layer board". Through-hole pads and vias then pass through all four.

A board also takes a solder-mask colour (green, purple, red, yellow, blue, white, black), keep-out areas where chosen nets may not run, and solid copper regions.

autoroute and pour

Ask the modeler for an Autoroute step. It lays tracks between the pads that the netlist says should join. It routes on front and back copper at 45°, uses vias between them, and keeps your hand-drawn copper. You choose track width and spacing per net, and can keep a pair of nets together as a differential pair.

Every track it keeps is re-measured against the DRC's clearance rules. When it cannot finish a connection it names the nets, where, and what boxed them in. A net too wide for a gap is laid thin and reported as thin.

Pour fills a layer with a net, usually ground, with thermal spokes and stitching vias.

check it

DRC (hotkey <kbd>D</kbd>) marks clearance, minimum width, board edge, unrouted connections and thin tracks. It also checks courtyards: two parts on one side may not overlap, and you can set a minimum gap between them. A courtyard is only as good as the footprint's outline. If a part's body is bigger than its footprint box, the check cannot see the overlap.

The ERC and DRC panels list each marker.

simulate

Simulate runs ngspice on the schematic, in your tab. Pick an analysis: OP, Transient, AC or DC sweep. Add Sources & loads (a source is named V… or I… with a SPICE value like SIN(0 325 50)), choose Probes, and read Results. Component values like 4k7 and 2M2 are understood. Diodes and transistors take a built-in approximate model by name, or you paste your own .model.

Models are approximations: use them for a first check of a rail, a filter or a driver, not to sign off a design.

export

Open Fab outputs to see what the order will cost, or use Export in the top bar. The board gives you:

export	what it is
Gerber	a zip of copper, mask, silk, outline and paste layers (front and back), plus plated and unplated drill files
Drill	one Excellon file with every hole
BOM	CSV in JLCPCB's columns: Comment, Designator, Footprint, Quantity, Manufacturer, MPN, LCSC Part #
Pick & place	CSV with Designator, Mid X, Mid Y, Layer, Rotation
KiCad project	a zip with the board, the schematic, its libraries, net classes and design rules
Netlist JSON, SVG	the connectivity, and a drawing

The cost estimate in Fab outputs prices a board run with or without assembly from a dated price table. Surface-finish, thickness and gold-finger surcharges are guesses, and it is not a live quote.

to and from KiCad

The KiCad zip opens in KiCad 8, 9 and 10. Pours become zones that KiCad refills.

To go the other way, drop a .kicad_pcb file, or a zip containing one, on the canvas. ixi makes a new model in PCB layout with an Import KiCad step. A schematic on its own, without a board, is not imported yet.

limits & good to know

2 or 4 copper layers · 40 pins per header symbol · 64 keep-outs · 256 copper regions · 120 s autoroute budget. Simulation, routing and DRC run in an open tab; a pixie asking for them while none is open waits for one.

related

• packaging: the carton your board ships in
• assembly and motion: place the board in its case and animate the build
• variants and checks: check the board against its enclosure
• overview
• the cassette use case